This invention relates generally to test circuitry and more particularly to test circuitry adapted for testing integrated circuits.
As is known in the art, a simple test circuit merely includes a source of a known voltage which is fed to a circuit under test. One such an arrangement is shown in FIG. 1 where the device under test (DUT) is an analog to digital converter (ADC). In this very simple case, the test voltage is applied to the DUT and it is assumed that the voltage on the input pins is equal to the applied test voltage, to within some acceptable tolerance. Thus, since here the DUT is an analog to digital converter, with a known test voltage applied to the converter, the ADC should, if operating properly, produce a digital output corresponding to the applied test voltage. There are, however, a number of reasons why the applied test voltage does not appear at the input pins of the DUT. These include noise, magnetic or electrical coupling of other signals onto the wires joining the test voltage source to the pins of the DUT. In addition, the path from the test voltage source to the pins of the DUT will be comprised of many junctions where dissimilar metals make contact with each other. Each of these junctions will exhibit an electrical potential difference that is a repeatable function of temperature. For example, the sources include: the pins in the socket with the legs of the DUT; the gold pads onto which the socket may sit; the tracks on the test board (used to customize the test resources to the particular DUT); the plated through holes on that board; and, pogo pins used to connect the board to the tester. Each junction is, in effect, a thermocouple. As the DUT temperature is changed from room temperature, the voltage appearing at the DUT pins will change in response to these thermocouples so that the voltage at the DUT pins is no longer the applied test voltage.
More particularly, commonly used temperatures in integrated circuit testing are from xe2x88x9255xc2x0 C. to +125xc2x0 C. This means that while the test voltage remains at room temperature (e.g., 25xc2x0 C.), the DUT may be at any temperature from xe2x88x9255xc2x0 C. to +125xc2x0 C. Thus, considering FIG. 1, the voltage V1 and V2 represent the potential from such thermocouple effect. Consequently, the voltage measured by the ADC will be VADC=VTESTxe2x88x92(V1xe2x88x92V2), where the applied test voltage is VTEST rather than such ADC producing a digital output representative of VTEST.
One technique used to remove this source of error is shown in FIG. 2. Here, a digital voltmeter (DVM) is added to measure the voltage at the pins of the DUT. This solution is only partially effective because the DVM will also be at room temperature while the DUT may be at a much higher or lower temperature. Thus, the leads from the DVM to the DUT will suffer from the thermal EMFs (i.e., produce thermocouple effects) described above and represented in FIG. 2 as V3 and V4. Thus, referring to FIG. 2, the voltage, VACD, measured by the ADC will be VACD=VTESTxe2x88x92(V1xe2x88x92V2) but the voltage measured by the DVM will be VDVM=VTESTxe2x88x92(V1xe2x88x92V2)xe2x88x92(V4xe2x88x92V3). Thus, there will be an error equal to (V4xe2x88x92V3).
Variations on these techniques place great effort into the differential nature of the test voltage source and DVM leads in order to cancel out these thermal EMFs. Other efforts rely on using undesirable long leads made from homogeneous materials so that no junction exists in the material across which the temperature change exists.
As is also known in the art, a drift test is generally required for an ADC. The drift performance of an ADC is measured by applying a test voltage at a known temperature, e.g., 25xc2x0 C., converting the test voltage to a corresponding digital word, and storing such word as a code, i.e., code25. The DUT temperature is then changed and another conversion is performed and the digital word is stored as codeT. It is assumed that the input test voltage remains unchanged and that any change in the output code is due to the drift of the DUT. The drift component is then specified as:
DUT drift=(codeTxe2x88x92code25)*DUTxe2x80x94lsb/(Txe2x88x9225);
Where:
DUT_lsb is the conversion factor for the ADC output code into volts; and
T is temperature in degrees Centigrade.
This gives a result in volts per degree C. Sometimes the drift result will be returned in PPM per degree C. which is a similar calculation. Drift is normally specified separately for positive and negative changes in temperatures around 25xc2x0 C.
One method of applying a known voltage is to use an xe2x80x9cinternal shortxe2x80x9d test mode. This mode allowed the generation of a very stable zero volts by literally shorting the ADC inputs together internally to the DUT and connecting them to an internal pin which can be used as a common mode voltage. Thus, referring to FIG. 1, the two inputs to the ADC are shorted together.
However, measuring drift with a non-zero input then still remains a challenge. In particular, the problem of full-scale, negative full-scale, and gain drifts remain. To ensure that an external input remains stable as the DUT temperature is increased, the ADC evaluation used a dedicated printed circuit board which contained the minimum number of external components. This printed circuit board was enclosed in a sealed box whose temperature could be raised or lowered by an external temperature forcing system. On the printed circuit board sat the DUT so that as the DUT temperature was raised so was the temperature of the printed circuit board. The test voltage source is applied to the DUT through a series of long cables. One end of the cable sat at ambient temperature and the other end was at the temperature of the DUT. With shorter cables, the temperature gradient on the cable would be large and the junctions at either end could lead to fluctuating thermal EMFs.
One method used to perform a drift test is to generate the analog input with a resistor divider on the printed circuit board which sits in the temperature chamber. One end of the resistor divider goes to ground and the other to a reference potential. This makes any change in the reference potential to the DUT appear ratiometric on the analog input and removes the effect of such change in reference potential. However, this method is not entirely satisfactory because in order to generate full scale on a gain of two setting, equal valued resistors are required in order to generate half the reference potential. These resistors will have a temperature coefficient. Therefore, their resistance will change with temperature.
In accordance with the present invention a circuit is provided for testing an integrated circuit. The circuit includes: a chop circuit; a source of a test signal coupled to a first pin and a second pin of the integrated circuit; and a test signal measuring device to measure the test signal coupled to a third pin and a fourth pin of the integrated circuit. A chop circuit controller is provided for producing a control signal, for example a bi-level signal, and for feeding such control signal to the chop circuit and the test signal measuring device. During one period of time, in response to the control signal, the chop circuit couples the first pin to the third pin and the second pin to the fourth pin. During another period of time, in response to the control signal, the chop circuit couples the first pin to the fourth pin and the second pin to the third pin. A difference between a measurement made by the measuring device during the first-mentioned period of time and a measurement made during the later-mentioned period of time is calculated and divided by two.
With such an arrangement, the test signal measuring device monitors the voltage at the pins of the integrated circuit under test (i.e., DUT) and performs calculations on such measurements which null any thermocouple produced EMF effects on leads between the test signal source and the pins of the DUT and leads between the test measuring device and pins of the DUT.
Further, with such an arrangement, no special board is required. Here, the test signal source can drift with temperature and the drift of the DUT under the test can still be accurately measured.
Typically, the chop circuit is disposed on the integrated circuit.
In accordance with another feature of the invention, circuitry is provided for testing an integrated circuit. The circuit includes a chop circuit; a source of a test signal coupled to the integrated circuit; a test signal measuring device to measure the test signal coupled to the integrated circuit; and, a chop circuit controller. The controller produces a control signal. In response to such control signal, the chop circuit couples the test signal source to the test signal measuring device with a first polarity during one period of time and couples the test signal source to the test signal measuring device with an opposite polarity during another period of time.
In accordance with another feature of the invention, a circuit is provided for testing an integrated circuit. The circuit includes: a chop circuit; a source of a test signal coupled to a first pair of pins of the integrated circuit; a test signal measuring device to measure the test signal coupled to a second pair of pins of the integrated circuit; and, a chop circuit controller for producing a control signal and for feeding such control signal to the chop circuit and the test signal measuring device. In response to such control signal, the chop circuit, during one period of time couples the first pair of pins to the second pair of pins with a first polarity and during another period of time couples the first pair of pins to the second pair of pins with an opposite polarity.
In one embodiment of the invention the integrated circuit includes an analog to digital converter and wherein the chopper circuit is coupled between the first pair and the analog to digital converter.
In another embodiment of the invention, the integrated circuit includes an analog to digital converter and wherein the chopper circuit is coupled between the first pair and the test signal measuring device.
In accordance with still another feature of the invention, a method is provided for testing an integrated circuit. The method includes: coupling a source of a test signal to a first pair of pins of the integrated circuit; coupling a test signal measuring device to measure the test signal to a second pair of pins of the integrated circuit; and coupling the first pair of pins to the second pair of pins with a first polarity during one period of time and coupling the first pair of pins to the second pair of pins with an opposite polarity during another period of time.
In one embodiment, the method includes subtracting a signal measured by the measuring device when the first pair of pins is coupled to the second pair of pins with the first polarity from a signal measured by the measuring device when the first pair is coupled to the second pair of pins with the opposite polarity.